Residue Arithmetic A Tutorial with Examples

Authors:
F. J. Taylor
Affiliations:
University of Florida
Venue:
Computer
Year:
1984

Citing 0
Cited 12

Complex Integer to Complex Residue Encoding

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An efficient design of residue to binary converter for four moduli set (2n-1,2n+1,22n-2,22n+1-3) based on new CRT II

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Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A generalization of a fast RNS conversion for a new 4-modulus base

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An RNS implementation of an Fpelliptic curve point multiplier

IEEE Transactions on Circuits and Systems Part I: Regular Papers
High-radix residue arithmetic bases for low-power DSP systems

DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
A low-complexity high-radix RNS multiplier

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient reverse converter designs for the new 4-moduli sets {2n - 1, 2n, 2n + 1, 22n+1 - 1} and {2n - 1, 2n + 1, 22n, 22n + 1} based on new CRTs

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Journal of Signal Processing Systems
Systematic design of full adder-based architectures for convolution

ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system

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"Floating point RNS": a new concept for designing the MAC unit of digital signal processor

ACM SIGARCH Computer Architecture News

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Abstract

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