The FFT fundamentals and concepts
The FFT fundamentals and concepts
Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Digital signal analysis
Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
DFT/FFT and Convolution Algorithms: Theory and Implementation
DFT/FFT and Convolution Algorithms: Theory and Implementation
Fast Transforms: Algorithms, Analyses, Applications
Fast Transforms: Algorithms, Analyses, Applications
Number Theory in Digital Signal Processing
Number Theory in Digital Signal Processing
COBRA: An 1.2 Million Transistor Expandable Column FFT Chip
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Computing 2-D DFTs Using FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Multiplierless implementation of rotators and FFTs
EURASIP Journal on Applied Signal Processing
A high-speed CMOS implementation of the Winograd Fourier transformalgorithm
IEEE Transactions on Signal Processing
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It has recently been shown that the n-dimensional reduced adder graph (RAG-n) technique is beneficial for many DSP applications such as for FIR and IIR filters, where multipliers can be grouped in multiplier blocks. This paper highlights the importance of DFT and FFT as DSP objects and also explores how the RAG-n technique can be applied to these algorithms. This RAG-n DFT will be shown to be of low complexity and possess an attractively regular VLSI data flow when implemented with the Rader DFT algorithm or the Bluestein chirp-z algorithm. ASIC synthesis data are provided and demonstrate the low complexity and high speed of the design when compared to other alternatives.