Fast multiplierless approximations of the DCT with the liftingscheme
IEEE Transactions on Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast discrete Fourier transform computations using the reduced adder graph technique
EURASIP Journal on Applied Signal Processing
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Complex rotators are used in many important signal processing applications, including Cooley-Tukey and split-radix FFT algorithms. This paper presents methods for designing multiplierless implementations of fixed-point rotators and FFTs, in which multiplications are replaced by additions, subtractions, and shifts. These methods minimise the adder-cost (the number of additions and subtractions), while achieving a specified level of accuracy. FFT designs based on multiplierless rotators are compared with designs based on the multiplierless implementation of DFT matrix multiplication. These techniques make possible VLSI implementations of rotators and FFTs which could achieve very high speed and/or power efficiency. The methods can be used to provide any chosen accuracy; examples are presented for 12 to 26 bit accuracy. On average, rotators are shown to be implementable using 10, 12, or 15 adders to achieve accuracies of 12, 16, or 20 bits, respectively.