Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
A Residue Arithmetic Extension for Reliable Scientific Computation
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Introducing Core-Based System Design
IEEE Design & Test
Automating the Design of SOCs Using Cores
IEEE Design & Test
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Full RNS Implementation of RSA
IEEE Transactions on Computers
Error Correcting Properties of Redundant Residue Number Systems
IEEE Transactions on Computers
Error Correction in Residue Arithmetic
IEEE Transactions on Computers
Implementation issues of the two-level residue number system withpairs of conjugate moduli
IEEE Transactions on Signal Processing
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Residue Number System (RNS) is an integer and non weighted number system that is useful tool for Digital Signal Processing (DSP) since it can support parallel, carry-free, high-speed and low power arithmetic. Redundant Residue Number System is an extension of RNS which also supports error detection and correction. The Multi-Level Residue Number System uses the new Residue Number System for each modulo, so in the relation of decreasing modulo the speed of operation is increased. By the combination of those systems we purpose a new numeric system which supports parallel and high speed computations, restricted carry propagation and reliable communications. This system also supports high error detection and correction capabilities. Because of design challenge of future nanoscale regime, on-chip networks have been proposed as a solution. As technology scales toward deep submicron, on-chip interconnects are becoming more sensitive to noise sources such as crosstalk or power supply noise. Therefore error detection and correction is one of the major properties of future on-chip micro networks. In this paper we propose using Redundant Multi-Level Residue Number System to increase the data transmission reliability in on-chip networks. This method achieves more optimizations in the terms of data security, error detection and correction, high speed data transmission and computation.