Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
IEEE Transactions on Computers
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Reliable And Secure Chip Level Communication By Residue Number System Code
Journal of Integrated Design & Process Science
Fast modulo 2n+1 multi-operand adders and residue generators
Integration, the VLSI Journal
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Efficient architectures for modulo 2n-1 squarers
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Improved area-efficient weighted modulo 2n+ 1 adder design with simple correction schemes
IEEE Transactions on Circuits and Systems II: Express Briefs
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
On the design of modulo 2n+1 dot product and generalized multiply-add units
Computers and Electrical Engineering
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
Integration, the VLSI Journal
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Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices. A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper. The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver. A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced. The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth. Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%.