The area-time complexity of a VLSI digital filter using residue number systems
Computers and Electrical Engineering
Residue Number Systems: Algorithms and Architectures
Residue Number Systems: Algorithms and Architectures
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
Journal of VLSI Signal Processing Systems
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
RDSP: A RISC DSP based on Residue Number System
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
A Full RNS Implementation of RSA
IEEE Transactions on Computers
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
IEEE Micro
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Residue Number Systems: Theory and Implementation
Residue Number Systems: Theory and Implementation
Yet Faster Ray-Triangle Intersection (Using SSE4)
IEEE Transactions on Visualization and Computer Graphics
Efficient Online Self-Checking Modulo 2^n+1 Multiplier Design
IEEE Transactions on Computers
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Video filtering with Fermat number theoretic transforms using residue number system
IEEE Transactions on Circuits and Systems for Video Technology
Efficient Modulo $2^{n}+1$ Multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical evaluation of a time- and energy-efficient security protocol for IP-enabled sensors
Computers and Electrical Engineering
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In this work, modulo 2^n+1 fused architectures of dot product and generalized multiply-add units for operands in the weighted representation are proposed. According to our algorithm, the partial products and the additive operands are efficiently added using inverted end around carry-save adder trees. This approach results to large savings on delay, area and power compared to using discrete units. Optimization techniques and implementation results for units with practical interest are also given. The proposed modulo 2^n+1 arithmetic units can be utilized in all applications where the residue number system is used for the implementation of digital signal processing and cryptography algorithms.