Fast Base Extension Using a Redundant Modulus in RNS
IEEE Transactions on Computers
A survey of hardware implementations of RSA (abstract)
CRYPTO '89 Proceedings on Advances in cryptology
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Modulo Reduction in Residue Number Systems
IEEE Transactions on Parallel and Distributed Systems
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Modular Multiplication and Base Extensions in Residue Number Systems
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Cox-Rower architecture for fast parallel montgomery multiplication
EUROCRYPT'00 Proceedings of the 19th international conference on Theory and application of cryptographic techniques
A generalization of a fast RNS conversion for a new 4-modulus base
IEEE Transactions on Circuits and Systems II: Express Briefs
An RNS implementation of an Fpelliptic curve point multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reliable And Secure Chip Level Communication By Residue Number System Code
Journal of Integrated Design & Process Science
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Revisiting sum of residues modular multiplication
Journal of Electrical and Computer Engineering
Efficient modulo 2n±1 squarers
Integration, the VLSI Journal
An efficient parity detection technique using the two-moduli set {2h-1,2h+1}
Information Sciences: an International Journal
Area-time efficient multi-modulus adders and their applications
Microprocessors & Microsystems
On the design of modulo 2n+1 dot product and generalized multiply-add units
Computers and Electrical Engineering
On the design of modulo 2n-1 cubing units
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Improving modular inversion in RNS using the plus-minus method
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
Integration, the VLSI Journal
Hi-index | 14.98 |
Abstract--We present the first implementation of RSA in the Residue Number System (RNS) which does not require any conversion, either from radix to RNS beforehand or RNS to radix afterward. Our solution is based on an optimized RNS version of Montgomery multiplication. Thanks to the RNS, the proposed algorithms are highly parallelizable and seem then well suited to hardware implementations. We give the computational procedure both parties must follow in order to recover the correct result at the end of the transaction (encryption or signature).