Efficient modulo 2n±1 squarers

Authors:
D. Bakalis;H. T. Vergos;A. Spyrou
Affiliations:
Physics Department, University of Patras, 26 500, Greece;Computer Engineering & Informatics Department, University of Patras, 26 500, Greece;Computer Engineering & Informatics Department, University of Patras, 26 500, Greece
Venue:
Integration, the VLSI Journal
Year:
2011

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Abstract

Modulo 2^n+/-1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way, architectures for their design that are based on the radix-4 modified Booth encoding. For the modulo 2^n+1 case, both the normal and the diminished-one representations are considered. Experimental results show that the proposed squarers offer significant savings in the implementation area over previous proposals that can reach up to 38% for sufficiently large operand widths, while in many cases a small improvement in execution delay can also be achieved.