Regular, area-time efficient carry-lookahead adders
Journal of Parallel and Distributed Computing
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Design and implementation of a high-speed reconfigurable modular arithmetic unit
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Efficient modulo 2n±1 squarers
Integration, the VLSI Journal
A Reconfigurable Channel Filter for Software Defined Radio Using RNS
Journal of Signal Processing Systems
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The modulo (2n + 1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a modulo (2n + 1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth's algorithm to the modulo (2n + 1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier's calculation delay and is suitable for VLSI implementation for moderate and large n (n驴 16).