IEEE Transactions on Computers
Signed-Digit Architecture for Residue to Binary Transformation
IEEE Transactions on Computers
A Simplified Architecture for Modulo (2n + 1) Multiplication
IEEE Transactions on Computers
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
A New Technique for Fast Number Comparison in the Residue Number System
IEEE Transactions on Computers
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Residue number system to binary converter for the moduli set (2n-1, 2n - 1, 2n + 1)
Journal of Systems Architecture: the EUROMICRO Journal
An arithmetic residue to binary conversion technique
Integration, the VLSI Journal
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS
IEEE Transactions on Computers
A new high dynamic range moduli set with efficient reverse converter
Computers & Mathematics with Applications
Optimum RNS sign detection algorithm using MRC-II with special moduli set
Journal of Systems Architecture: the EUROMICRO Journal
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Core function of an RNS number with no ambiguity
Computers & Mathematics with Applications
High-radix residue arithmetic bases for low-power DSP systems
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Residue arithmetic for designing low-power multiply-add units
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
| Hi-index | 14.99 |
A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we are introducing a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2n+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay.