Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Residue arithmetic for a fault-tolerant multiplier: the choice of the best tripe of bases
Microprocessing and Microprogramming - Special issue short notes
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
VLSI Implementation of new arithmetic residue to binary decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. This is achieved by introducing a general moduli set Sk$$S^k=\left\{ {2^m-1,\,\,2^{2^0m}+1,\,\,2^{2^1m}+1,\,\,2^{2^2m}+1,\,\,\ldots ,\, \,2^{2^km}+1} \right\}$$for Residue Number System (RNS) applications. Residue to binary converter architectures based on moduli sets S0 = {2m驴 1, 2m + 1} and S1 = {2m驴 1, 2m + 1, 22m + 1} are developed. The conversion procedure is performed in the following three levels:驴驴驴驴residue to signed-digit,驴驴驴驴signed-digit to binary,驴驴驴驴end-around carry addition/subtraction.In the first level of operation, the signed-digit representation of the CRT equation is realized by using redundant adder/subtractor blocks. Here, the necessary embedded multiplications are replaced by simple shift-left operations and the carry propagation is totally eliminated. In the second level, the redundant representation of CRT is directly converted to binary format. Finally, an end-around carry (EAC) addition/subtraction is performed to obtain the result at the third level of operation. The proposed architectures are simple, fast, free of memory blocks and modulo adders.