High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Systolic Modular Multiplication
IEEE Transactions on Computers
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
An RNS Montgomery Modular Multiplication Algorithm
IEEE Transactions on Computers
Linear Algorithms That Are Efficiently Parallelized to Time O(logn)
Linear Algorithms That Are Efficiently Parallelized to Time O(logn)
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies
Journal of VLSI Signal Processing Systems
Fast modular exponentiation of large numbers with large exponents
Journal of Systems Architecture: the EUROMICRO Journal
An arithmetic residue to binary conversion technique
Integration, the VLSI Journal
How to fake an RSA signature by encoding modular root finding as a SAT problem
Discrete Applied Mathematics - The renesse issue on satisfiability
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
VLSI Implementation of new arithmetic residue to binary decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lowering power in an experimental RISC processor
Microprocessors & Microsystems
Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS
IEEE Transactions on Computers
A low-complexity high-radix RNS multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Hierarchical residue number systems with small moduli and simple converters
International Journal of Applied Mathematics and Computer Science - Semantic Knowledge Engineering
Performance analysis of a FPGA based novel binary and DBNS multiplier
ACM SIGARCH Computer Architecture News
| Hi-index | 14.99 |
Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In realizing these multipliers, ROM-based structures are more efficient for small moduli. Due to the exponential growth of ROM sizes, implementations with arithmetic components are more suitable for medium and large moduli. This paper presents a new modular multiplier that can deal efficiently with medium and large size moduli. The design of this modular multiplier that multiplies two $n$ bit residue digits consists, basically, of a $(n\times n)$ binary multiplier, a $((n-1-k)\times k)$ binary multiplier $(k