Theory and Applications of the Double-Base Number System
IEEE Transactions on Computers
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
Computer Architecture and Organization
Computer Architecture and Organization
An array processor for inner product computations using a Fermat number ALU
ASAP '95 Proceedings of the IEEE International Conference on Application Specific Array Processors
Modified Booth Modulo 2^n-1 Multipliers
IEEE Transactions on Computers
The impact of software radio on wireless networking
ACM SIGMOBILE Mobile Computing and Communications Review
Radio Processor - A New Reconfigurable Architecture for Software Defined Radio
ICCSIT '08 Proceedings of the 2008 International Conference on Computer Science and Information Technology
An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio
ICETC '09 Proceedings of the 2009 International Conference on Education Technology and Computer
A novel architecture for conversion of binary to single digit double base numbers
ACM SIGARCH Computer Architecture News
IEEE Journal on Selected Areas in Communications
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Designing high performance Software Defined Radio (SDR) with low power and flexibility is a major challenge. While the high performance DSP processors are unable to meet the speed requirements of these SDRs, System on chips (SOCs) are also not suitable because of their limited flexibility. Recently dynamically reconfigurable FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions efficiently. Since basic intention of an SDR is to implement different modulation / demodulation schemes and basic building blocks for such schemes are signal processing functions, FPGAs have become an important component for implementing these. However, the effectiveness of such an approach with respect to cost, performance and flexibility need to be examined. Double Base Number Systems (DBNS) have been gaining attention for compute intensive applications in signal processing because of their higher performance in arithmetic operations in general and particularly multiplication. Keeping these issues in view, this paper aims to present a new Software defined Radio. To Enhance the performance of the proposed architecture , analysis have been done employing both single index and multiple indices DBNS multipliers. Experiments and analysis on performance have also been done with its binary counterpart. Both DBNS and binary based architecture were implemented on Xilinx virtex iv FPGA using xilinx ISE 9.1 i.