Exploiting temporal parallelism for software-only video effects processing
MULTIMEDIA '98 Proceedings of the sixth ACM international conference on Multimedia
An algorithm for modular exponentiation
Information Processing Letters
Theory and Applications of the Double-Base Number System
IEEE Transactions on Computers
Residue Number Systems: Algorithms and Architectures
Residue Number Systems: Algorithms and Architectures
Computer Architecture and Organization
Computer Architecture and Organization
An arithmetic residue to binary conversion technique
Integration, the VLSI Journal
The Design of Optimal Systolic Arrays
IEEE Transactions on Computers
An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words
IEEE Transactions on Computers
On Control Memory Minimization in Microprogrammed Digital Computers
IEEE Transactions on Computers
Conversion of binary to single-term triple base numbers for DSP applications
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
Performance analysis of a FPGA based novel binary and DBNS multiplier
ACM SIGARCH Computer Architecture News
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Double base number systems are increasingly attractive for many compute intensive applications especially in signal processing because of their capabilities of handling arithmetic operations efficiently. However, the complexity involved in converting binary to DBNS becomes a major bottleneck and the efficiency of performance goes down drastically due to the complexity involved in conversion . Since complexity of multi digit DBNS multiplications and additions increases with the number of digits ( index i ,j) ,in this paper a novel conversion scheme has been proposed where a given binary number will be converted to a single digit (index i ,j) double base number . The proposed scheme not only reduces the hardware complexity of the arithmetic operations but also reduces the time of execution.