A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique

Authors:
Satrughna Singha;Aniruddha Ghosh;Amitabha Sinha
Affiliations:
JIS College of Engineering, Kalyani, Nadia, West Bengal, India;Calcutta Institute of Technology, Uluberia, West Bengal, India;West Bengal University of Technology, Salt Lake, Kolkata, India
Venue:
ACM SIGARCH Computer Architecture News
Year:
2012

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Abstract

Compute intensive signal Processing Algorithms demand efficient execution of high performance arithmetic operations. Since, double base number system (DBNS) offers high performance arithmetic units, it is gaining attention to many researchers .However, the advantage of DBNS can not be exploited due to large conversion time from binary to DBNS. Keeping this issue in view, this paper presents a novel conversion scheme using parallel search technique.