Complexity of Matrix Product on a Class of Orthogonally Connected Systolic Arrays
IEEE Transactions on Computers
Mapping Homogeneous Graphs on Linear Arrays
IEEE Transactions on Computers
The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A novel architecture for conversion of binary to single digit double base numbers
ACM SIGARCH Computer Architecture News
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Conventional design of systolic arrays is based on the mapping of an algorithm onto an interconnection of processing elements in a VLSI chip. This mapping is done in an ad hoc manner, and the resulting configuration usually represents a feasible but suboptimal design. In this paper, systolic arrays are characterized by three classes of parameters: the velocities of data flows, the spatial distributions of data, and the periods of computation. By relating these parameters in constraint equations that govern the correctness of the design, the design is formulated into an optimization problem. The size of the search space is a polynomial of the problem size, and a methodology to systematically search and reduce this space and to obtain the optimal design is proposed. Some examples of applying the method, including matrix multiplication, finite impulse response filtering, deconvolution, and triangular-matrix inversion, are given.