Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
VLSI array processors
The Design of Optimal Systolic Arrays
IEEE Transactions on Computers
Semisystolic Array Implementation of Circular, Skew Circular, and Linear Convolutions
IEEE Transactions on Computers
Partitioned Matrix Algorithms for VLSI Arithmetic Systems
IEEE Transactions on Computers
Computer
Efficient bit-level systolic array implementation of FIR and IIR digital filters
IEEE Journal on Selected Areas in Communications
Designing of processor-time optimal systolic arrays for band matrix-vector multiplication
Computers & Mathematics with Applications
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A simple method for obtaining problem-size independent systolic arrays from a certain type of problem-size dependent systolic arrays is presented. The resulting array is fully fault-tolerant in the sense that a faulty processing element can be bypassed and the same problem of the original size can be solved. Such an array may outperform another larger array of the same type under certain conditions; this phenomenon is called the array size anomaly. Matrix-vector multiplication is used as an example problem solved by the systolic arrays. Two systolic arrays of different sizes for computing a given convolution are then derived and compared.