Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
Systematic design approaches for algorithmically specified systolic arrays
Computer architecture
Automating the design of systolic arrays
Integration, the VLSI Journal
Computer
Folded semi-systolic FIR Filter architecture with changeable folding factor
Neural, Parallel & Scientific Computations
Designing processor-time optimal systolic configurations
Highly parallel computaions
The Journal of Supercomputing
The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Synthesis of a unidirectional systolic array for matrix-vector multiplication
Mathematical and Computer Modelling: An International Journal
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This paper describes the procedure for synthesizing processor-time optimal linear (1D) systolic arrays for band matrix-vector multiplication. The procedure is based on data dependence approach. By the described procedure, three different systolic arrays, denoted as S1, S2 and S3, are obtained. The first two are obtained by the orthogonal directions. The array S3 is a bidirectional linear array of Kung's type. The procedure enables us to obtain optimal bidirectional 1D systolic array where data streams enter the array in consecutive time instances which leads to decreasing of execution time and increasing of PEs' utilization