VLSI array processors
Massive parallel processing for matrix multiplication: a systolic approach
Highly parallel computaions
Computer
Designing of processor-time optimal systolic arrays for band matrix-vector multiplication
Computers & Mathematics with Applications
A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method
The Journal of Supercomputing
Synthesis of space optimal systolic arrays for band matrix-vector multiplication
The Journal of Supercomputing
WSEAS Transactions on Signal Processing
Journal of Systems Architecture: the EUROMICRO Journal
A class of fault-tolerant systolic arrays for matrix multiplication
Mathematical and Computer Modelling: An International Journal
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In this paper we present a procedure, based on data dependencies and space-time transformations of index space, to design a unidirectional linear systolic array (ULSA) for computing a matrix-vector product. The obtained array is optimal with respect to the number of processing elements (PEs) for a given problem size. The execution time of the array is the minimal possible for that number of PEs. To achieve this, we first derive an appropriate systolic algorithm for ULSA synthesis. In order to design a ULSA with the optimal number of PEs we then perform an accommodation of the index space to the projection direction vector. The performance of the synthesized array is discussed and compared with the bidirectional linear SA. Finally, we demonstrate how this array can be used to compute the correlation of two given sequences.