Massive parallel processing for matrix multiplication: a systolic approach

Authors:
D. J. Evans;C. R. Wan
Affiliations:
Department of Computing, Nottinham Trent University, Nottingham, U.K.;School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Venue:
Highly parallel computaions
Year:
2001

Citing 4
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Abstract

In this chapter, we have designed nineteen systolic arrays for matrix multiplication under the framework of the systolic synthesis method using regular iterative algorithm (RIA) representation. Then we define different systolic array performance measures in order to evaluate the systolic designs. The performance of the designed systolic arrays is analysed in detail and this allows the comparison among the different systolic designs.