High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Algorithms for Iterative Array Multiplication
IEEE Transactions on Computers
Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Linear Algorithms That Are Efficiently Parallelized to Time O(logn)
Linear Algorithms That Are Efficiently Parallelized to Time O(logn)
A complexity theory for VLSI
A new parallel multiplication algorithm and its VLSI implementation
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I/sup 2/L Technology
IEEE Transactions on Computers
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
VLSI Implementation of Modulo Multiplication Using Carry Free Addition
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant differences in time.