A new parallel multiplication algorithm and its VLSI implementation

Authors:
Bhabani P. Sinha;Pradip K. Srimani
Affiliations:
Department of Computer Science, Southern Illinois University, Carbondale, IL;-
Venue:
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
Year:
1988

Citing 7
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Abstract

A new fast algorithm for parallel multiplication of two n-bit binary numbers has been presented in this paper. The proposed algorithm computes the product in 31og2n units of time of a single bit full-adder and is easily implemented on a suitable VLSI architecture using less than n(n + (1/2) log2n)/2 processing elements. The algorithm requires regular interconnection between only two types of cells and hence is very suitable for VLSI implementation. It can also be easily modified to handle two's complement numbers without any additional execution time.