High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
IEEE Transactions on Computers
Handbook of theoretical computer science (vol. A)
A survey of hardware implementations of RSA (abstract)
CRYPTO '89 Proceedings on Advances in cryptology
Modular exponentiation using recursive sums of residues
CRYPTO '89 Proceedings on Advances in cryptology
A fast modular-multiplication algorithm based on a higher radix
CRYPTO '89 Proceedings on Advances in cryptology
IEEE Transactions on Computers
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Systolic Modular Multiplication
CRYPTO '90 Proceedings of the 10th Annual International Cryptology Conference on Advances in Cryptology
Linear Algorithms That Are Efficiently Parallelized to Time O(logn)
Linear Algorithms That Are Efficiently Parallelized to Time O(logn)
New directions in cryptography
IEEE Transactions on Information Theory
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In this article we show how the technique of carry free addition can be used to get efficient algorithms for modulo multiplication. We present two algorithms and their VLSI implementations. The first algorithm runs in time O(n\log n) (for n bit numbers), has an AT^2 measure of O((n\log n)^3), and can be implemented using a systolic architecture. The second algorithm is a parallel modulo algorithm that uses table look up to speed up computation. The time complexity is O(\log n), the AT^2 measure is O((n\,\log n)^2), and it can also be implemented using a systolic architecture. Used with a O(\log n) multiplier, it can perform modulo multiplication in O(\log n) time. Both the algorithms have the advantage that the circuit is independent of the modulus N. Thus the same chip can be used for RSA cryptosystems with different moduli.