Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I/sup 2/L Technology

Authors:
M. De;B. P. Sinha
Affiliations:
-;-
Venue:
IEEE Transactions on Computers
Year:
1994

Citing 5
Cited 1

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

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Algorithms for Iterative Array Multiplication

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Designing efficient algorithms for parallel computers

Designing efficient algorithms for parallel computers
Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures

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Linear Algorithms That Are Efficiently Parallelized to Time O(logn)

Linear Algorithms That Are Efficiently Parallelized to Time O(logn)

Testing of a parallel ternary multiplier using I/sup 2/L logic

ATS '95 Proceedings of the 4th Asian Test Symposium

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Abstract

Presents an algorithm for parallel multiplication of two n-bit ternary numbers. This algorithm uses the technique of column compression and computes the product in (2 upper bound /spl lsqb/log/sub 2/n/spl rsqb/+2) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers.