Integer multiplication and division on the HP precision architecture
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Integer Multiplication and Division on the HP Precision Architecture
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
A multiple floating point coprocessor architecture
ACM SIGARCH Computer Architecture News
Mathematics and computer science at odds over real numbers
SIGCSE '91 Proceedings of the twenty-second SIGCSE technical symposium on Computer science education
IEEE Transactions on Computers
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
'Overturned-Stairs' Adder Trees and Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
New Multipliers Modulo 2/sup N/-1
IEEE Transactions on Computers - Special issue on computer arithmetic
Fast Division Using Accurate Quotient Approximations to Reduce the Number of Iterations
IEEE Transactions on Computers - Special issue on computer arithmetic
A Novel Division Algorithm for the Residue Number System
IEEE Transactions on Computers - Special issue on computer arithmetic
ELM-A Fast Addition Algorithm Discovered by a Program
IEEE Transactions on Computers
Decomposition of Complex Multipliers Using Polynomial Encoding
IEEE Transactions on Computers
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Hardware Starting Approximation Method and Its Application to the Square Root Operation
IEEE Transactions on Computers
Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
A multiple floating point coprocessor architecture
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
CMOS floating-point unit for the S/390 parallel enterprise server G4
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
A systolic multiplier unit and its VLSI design
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
On the Design of IEEE Compliant Floating Point Units
IEEE Transactions on Computers
Design of self-timed asynchronous Booth's multiplier
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
Multimedia Execution Hardware Accelerator
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
The MIPS R3010 Floating-Point Coprocessor
IEEE Micro
IEEE Micro
IEEE Transactions on Computers
Some Results on a SRT Type Division Scheme
IEEE Transactions on Computers
IEEE Transactions on Computers
Parallel High-Radix Nonrestoring Division
IEEE Transactions on Computers
High-Performance 3-1 Interlock Collapsing ALU's
IEEE Transactions on Computers
Over-Redundant Digit Sets and the Design of Digit-By-Digit Division Units
IEEE Transactions on Computers
Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
Division Using a Logarithmic-Exponential Transform to Form a Short Reciprocal
IEEE Transactions on Computers
Residue number system to binary converter for the moduli set (2n-1, 2n - 1, 2n + 1)
Journal of Systems Architecture: the EUROMICRO Journal
Bit-serial architecture for rank order and stack filters
Integration, the VLSI Journal
An arithmetic residue to binary conversion technique
Integration, the VLSI Journal
Parallel encrypted array multipliers
IBM Journal of Research and Development - Nanostructure technology
Systematic IEEE rounding method for high-speed floating-point multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Encyclopedia of Computer Science
Truncated Online Arithmetic with Applications to Communication Systems
IEEE Transactions on Computers
Information Sciences: an International Journal
The S/390 G5 floating-point unit
IBM Journal of Research and Development
A new VLSI architecture of parallel multiplier-accumulator based on radix-2 modified booth algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.05 |