Computer arithmetic algorithms
Computer arithmetic algorithms
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
Computer Architecture; A Designer's Text Based on a Generic RISC
Computer Architecture; A Designer's Text Based on a Generic RISC
167 MHz Radix-4 Floating Point Multiplier
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
How Many Logic Levels Does Floating-Point Addition Require?
ICCD '98 Proceedings of the International Conference on Computer Design
On fast IEEE rounding
Integration, the VLSI Journal
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Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm.