On the Design of IEEE Compliant Floating Point Units
IEEE Transactions on Computers
Proceedings of the 38th annual Design Automation Conference
Achieving maximum performance: a method for the verification of interlocked pipeline control logic
Proceedings of the 39th annual Design Automation Conference
Integration, the VLSI Journal
Solving the generalized mask constraint for test generation of binary floating point add operation
Theoretical Computer Science - Real numbers and computers
Formal Verification of the VAMP Floating Point Unit
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formalization of Cadence SPW Fixed-Point Arithmetic in HOL
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Efficient formal verification of pipelined processors with instruction queues
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Secondary Radix Recodings for Higher Radix Multipliers
IEEE Transactions on Computers
A parametric error analysis of Goldschmidt's division algorithm
Journal of Computer and System Sciences
Proceedings of the 10th international workshop on Formal methods for industrial critical systems
Formal Verification of the VAMP Floating Point Unit
Formal Methods in System Design
Dealing with I/O Devices in the Context of Pervasive System Verification
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Towards the Formal Verification of Lower System Layers in Automotive Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Towards the Formal Verification of a C0 Compiler: Code Generation and Implementation Correctnes
SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
Formal Verification of Pipelined Microprocessors with Delayed Branches
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Formalization of fixed-point arithmetic in HOL
Formal Methods in System Design
IBM POWER6 accelerators: VMX and DFU
IBM Journal of Research and Development
Pervasive Compiler Verification -- From Verified Programs to Verified Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
CVM -- A Verified Framework for Microkernel Programmers
Electronic Notes in Theoretical Computer Science (ENTCS)
Verified Process-Context Switch for C-Programmed Kernels
VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Journal of Automated Reasoning
Formal Verification of Gate-Level Computer Systems
CSR '09 Proceedings of the Fourth International Computer Science Symposium in Russia on Computer Science - Theory and Applications
CGADL: an architecture description language for coarse-grained reconfigurable arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the architecture of system verification environments
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Realistic worst-case execution time analysis in the context of pervasive system verification
Program analysis and compilation, theory and practice
Analysis of checksum-based execution schemes for pipelined processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
On the correctness of operating system kernels
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
System description: Combination of Isabelle/HOL with automatic tools
FroCoS'05 Proceedings of the 5th international conference on Frontiers of Combining Systems
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
On the verification of memory management mechanisms
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
On teaching fast adder designs: revisiting ladner & fischer
Theoretical Computer Science
RV'11 Proceedings of the Second international conference on Runtime verification
| Hi-index | 0.01 |