IBM POWER6 accelerators: VMX and DFU

Authors:
L. Eisen;J. W. Ward, III;H.-W. Tast;N. Mäding;J. Leenstra;S. M. Mueller;C. Jacobi;J. Preiss;E. M. Schwarz;S. R. Carlough
Affiliations:
IBM Systems and Technology Group, Austin, Texas;IBM Systems and Technology Group, Austin, Texas;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York
Venue:
IBM Journal of Research and Development
Year:
2007

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Abstract

The IBM POWER6™ microprocessor core includes two accelerators for increasing performance of specific workloads. The vector multimedia extension (VMX) provides a vector acceleration of graphic and scientific workloads. It provides single instructions that work on multiple data elements. The instructions separate a 128-bit vector into different components that are operated on concurrently. The decimal floating-point unit (DFU) provides acceleration of commercial workloads, more specifically, financial transactions. It provides a new number system that performs implicit rounding to decimal radix points, a feature essential to monetary transactions. The IBM POWER™ processor instruction set is substantially expanded with the addition of these two accelerators. The VMX architecture contains 176 instructions, while the DFU architecture adds 54 instructions to the base architecture. The IEEE 754R Binary Floating-Point Arithmetic Standard defines decimal floating-point formats, and the POWER6 processor--on which a substantial amount of area has been devoted to increasing performance of both scientific and commercial workloads--is the first commercial hardware implementation of this format.