Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Fast multiplication: algorithms and implementation
Fast multiplication: algorithms and implementation
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
The Case for a Redundant Format in Floating Point Arithmetic
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A High-Frequency Decimal Multiplier
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
High-Speed Multioperand Decimal Adders
IEEE Transactions on Computers
Decimal Multiplication with Efficient Partial Product Generation
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
A New Family of High.Performance Parallel Decimal Multipliers
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
Decimal Adder with Signed Digit Arithmetic
IEEE Transactions on Computers
IEEE Transactions on Computers
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach
IEEE Transactions on Computers
Compressor trees for decimal partial product reduction
Proceedings of the 18th ACM Great Lakes symposium on VLSI
IBM POWER6 accelerators: VMX and DFU
IBM Journal of Research and Development
Fully Redundant Decimal Arithmetic
ARITH '09 Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
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Decimal hardware arithmetic units have recently regained popularity, as there is now a high demand for high performance decimal arithmetic. We propose a novel method for carry-free addition of decimal numbers, where each equally weighted decimal digit pair of the two operands is partitioned into two weighted bit-sets. The arithmetic values of these bit-sets are evaluated, in parallel, for fast computation of the transfer digit and interim sum. In the proposed fully redundant adder (VS semi-redundant ones such as decimal carry-save adders) both operands and sum are redundant decimal numbers with overloaded decimal digit set [0, 15]. This adder is shown to improve upon the latest high performance similar works and outperform all the previous alike adders. However, there is a drawback that the adder logic cannot be efficiently adapted for subtraction. Nevertheless, this adder and its restricted-input varieties are shown to efficiently fit in the design of a parallel decimal multiplier. The two-to-one partial product reduction ratio that is attained via the proposed adder has lead to a VLSI-friendly recursive partial product reduction tree. Two alternative architectures for decimal multipliers are presented; one is slower, but area-improved, and the other one consumes more area, but is delay-improved. However, both are faster in comparison with previously reported parallel decimal multipliers. The area and latency comparisons are based on logical effort analysis under the same assumptions for all the evaluated adders and multipliers. Moreover, performance correctness of all the adders is checked via running exhaustive tests on the corresponding VHDL codes. For more reliable evaluation, we report the result of synthesizing these adders by Synopsys Design Compiler using TSMC 0.13@mm standard CMOS process under various time constrains.