A Framework for High-Level Synthesis of System-on-Chip Designs
MSE '05 Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education
Decimal Multiplication with Efficient Partial Product Generation
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
A New Family of High.Performance Parallel Decimal Multipliers
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
Error-free algorithm and architecture of radix-10 logarithmic converter
Computers and Electrical Engineering
| Hi-index | 0.00 |
Decimal multiplication has grown in interest due to the recent announcement of new IEEE 754R standards and the availability of high-speed decimal computation hardware. Prior research enabled partial products to be coded more efficiently for their use in radix 10 architectures. This paper clarifies previous techniques for partial product reduction using carry-save adders and presents a new 4:2 compressor structure. This new structure improves performance at the expense of more gates, however, regularity is introduced into the circuit to promote implementations in Very Large Scale Integration (VLSI) Designs. Results are presented and compared for several designs using a TSMC SCN6M $0.18 mu m feature size.