A digit serial algorithm for the integer power operation
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Compressor trees for decimal partial product reduction
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Fast false path identification based on functional unsensitizability using RTL information
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Impact of lithography-friendly circuit layout
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Placement for immunity of transient faults in cell-based design of nanometer circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical residue number systems with small moduli and simple converters
International Journal of Applied Mathematics and Computer Science - Semantic Knowledge Engineering
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A System on Chip (SoC) library for MOSIS scalable CMOS rules has been developed. It is intended for use with Synopsys and Cadence Design Systems Electronic Design Automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in System on Chip design through the MOSIS Educational Program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.