Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
A Framework for High-Level Synthesis of System-on-Chip Designs
MSE '05 Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education
Detailed placement for improved depth of focus and CD control
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Pattern sensitive placement for manufacturability
Proceedings of the 2007 international symposium on Physical design
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Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual wafer feature sizes. However, the circuit layout can be modified in a manner which can make it more lithography-friendly. These modifications are implemented as a series of perturbation iterations on the initial layout generated by the CAD tool. The iterations are performed based on estimates of the highest feature variations which are calculated offline for standard cell pairs and stored in a Look-up table (LUT). The iterations are directed by a Simulated Annealing algorithm. In the process we observe the impact of the iterations performed on the initial solution in terms of wirelength, vias and routing congestion. The procedure is validated on ISCAS85 benchmark circuits and a reduction of greater than 20% in the number of instances with the highest cell boundary feature variations is observed. The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2-7.8% respectively for different circuits.