Timing driven gate duplication

Authors:
Ankur Srivastava;Ryan Kastner;Chunhong Chen;Majid Sarrafzadeh
Affiliations:
Department of Electrical and Computer Engineering, University of Maryland, College Park, MD;Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of Windsor, ON N9B, 3P4 Canada;Department of Computer Science University of California Los Angeles, Los Angeles, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.