A performance driven macro-cell placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Minimum replication min-cut partitioning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Optimal replication for min-cut partitioning
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Min-cut replication in partitioned networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A replication cut for two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An exact algorithm for solving difficult detailed routing problems
Proceedings of the 2001 international symposium on Physical design
Timing driven gate duplication in technology independent phase
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing driven gate duplication: complexity issues and algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Eliminating wire crossings for molecular quantum-dot cellular automata implementation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simultaneous placement with clustering and duplication
Proceedings of the 41st annual Design Automation Conference
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This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing driven layout synthesis. Therefore, this paper presents a timing driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques.