Cell replication and redundancy elimination during placement for cycle time optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the global fanout optimization problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Evaluation and optimization of replication algorithms for logic bipartitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technology-based transformations
Logic Synthesis and Verification
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Techniques for improved placement-coupled logic replication
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Simultaneous placement with clustering and duplication
Proceedings of the 41st annual Design Automation Conference
A framework for layout-level logic restructuring
Proceedings of the 2008 international symposium on Physical design
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This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in minimizing the circuit delay has not been addressed. This paper studies the complexity issues in timing driven gate duplication and proposes an algorithm for solving the so called global gate duplication problem. Delay improvements over highly optimized results from SIS have been reported.