Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal replication for min-cut partitioning
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Cell replication and redundancy elimination during placement for cycle time optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing driven gate duplication: complexity issues and algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Addressing the timing closure problem by integrating logic optimization and placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
Performance-driven global placement via adaptive network characterization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Techniques for improved placement-coupled logic replication
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
DiCER: distributed and cost-effective redundancy for variation tolerance
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Eliminating wire crossings for molecular quantum-dot cellular automata implementation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simultaneous placement with clustering and duplication
Proceedings of the 41st annual Design Automation Conference
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A framework for layout-level logic restructuring
Proceedings of the 2008 international symposium on Physical design
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
Improving FPGA routability using network coding
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Logic replication for placement level timing optimization is studied in the context of FPGAs. We make the observation that critical paths are dominated by interconnect delay and are frequently highly circuitous. We propose a systematic replication technique to "straighten" such paths. The resulting algorithm has several components: cell selection, slot selection for a duplicate cell, fanout partitioning and placement legalization. This algorithm is described and promising preliminary experimental results are reported with up to 29% improvement in critical path delay.