Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Integrating logic retiming and register placement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multiway partitioning with pairwise movement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Placement driven retiming with a coupled edge timing model
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Multilevel global placement with retiming
Proceedings of the 40th annual Design Automation Conference
Continuous retiming: algorithms and applications
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Optimal clock period clustering for sequential circuits with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Edge separability-based circuit clustering with application to multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Delay minimization continues to be an important objective in the design of high-performance computing system. In this paper, we present an effective methodology to guide the delay optimization process of the mincut-based global placement via adaptive sequential network characterization. The contribution of this work is the development of a fully automated approach to determine critical parameters related to performance-driven multi-level partitioning-based global placement with retiming. We validate our approach by incorporating this adaptive method into a state-of-the-art global placer GEO. Our A-GEO, the adaptive version of GEO, achieves 67% maximum and 22% average delay improvement over GEO.