Understanding retiming through maximum average-weight cycles
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Continuous retiming: algorithms and applications
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal clock period clustering for sequential circuits with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constrained clock shifting for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
PipeRoute: a pipelining-aware router for FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Post-placement C-slow retiming for the xilinx virtex FPGA
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Sequential delay budgeting with interconnect prediction
Proceedings of the 2003 international workshop on System-level interconnect prediction
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
Incremental placement for layout driven optimizations on FPGAs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel global placement with retiming
Proceedings of the 40th annual Design Automation Conference
Incremental physical resynthesis for timing optimization
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Architecture-level synthesis for automatic interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Performance-driven global placement via adaptive network characterization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Incremental retiming for FPGA physical synthesis
Proceedings of the 42nd annual Design Automation Conference
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Armada: timing-driven pipeline-aware routing for FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A practical cut-based physical retiming algorithm for field programmable gate arrays
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An area-efficient timing closure technique for FPGAs using Shannon's expansion
Integration, the VLSI Journal
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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Retiming is a synchronous circuit transformation that can optimize the delay of a synchronous circuit by moving registers across combinational circuit elements. The combinational structure remains unchanged and the observable behavior of the circuit is identical to the original.In this paper, we address the problem of applying retiming techniques to circuits implemented in Field Programmable Gate Arrays (FPGAs). FPGAs contain prefabricated and configurable routing elements that allow us to easily implement a variety of circuits. However this interconnect contributes greatly to the overall delay in the implemented circuit. If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect. Our fundamental experiment is to determine whether there are any gains in tightly coupling retiming and placement so that the retiming algorithm has some estimate of the routing delays.Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features. This retiming algorithm may introduce extra registers into the circuit. These new registers need to be placed in some location in the FPGA. Retiming register placement is accomplished by a novel incremental clustering and placement algorithm. The incremental algorithm builds upon the placement of the non-retimed circuit to intelligently sift in the newly-introduced registers.In addition, we explore making the placement algorithms "retiming aware." These placement algorithms try to place logic blocks in such a way that the subsequent retiming produces better speed results. These techniques include the identification of retiming-critical cycles during placement.Our experiments show that the integration of retiming with placement results in 19% better clock periods in comparison to the application of retiming before the place and route steps.