A practical cut-based physical retiming algorithm for field programmable gate arrays

Authors:
Peter Suaris;Dongsheng Wang;Nan-Chi Chou
Affiliations:
Mentor Graphics Corporation, Wilsonville, OR;Mentor Graphics Corporation, Wilsonville, OR;Mentor Graphics Corporation, Wilsonville, OR
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 7
Cited 0

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Abstract

This paper presents a heuristic cut-based retiming algorithm for FPGA designs. It handles complex retiming constraints including timing, architectural and structural constraints; improves retimeability by incorporating logic resynthesis; and efficiently integrates with incremental placement. Thus, the algorithm improves timing compliance by allowing groups of registers to be rapidly retimed across blocks of combinational logic in the physical domain without violating any complex constraints. Experiments have shown that this algorithm can improve the performance of FPGA designs by 16% on average, while achieving a 61.7% speedup in terms of runtime compared with classic retiming algorithms.