A mixed-integer linear programming problem which is efficiently solvable
Journal of Algorithms
Introduction to algorithms
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Retiming with non-zero clock skew, variable register, and interconnect delay
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A fresh look at retiming via clock skew optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Retiming synchronous circuitry with imprecise delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
Integrating logic retiming and register placement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Asymptotically efficient retiming under setup and hold constraints
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On the optimization power of retiming and resynthesis transformations
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Simultaneous circuit partitioning/clustering with retiming for performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Retiming for DSM with area-delay trade-offs and delay constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Retiming of Circuits with Single Phase Transparent Latches
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Behavior and testability preservation under the retiming transformation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal clock period clustering for sequential circuits with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven register insertion in placement
Proceedings of the 2004 international symposium on Physical design
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A practical cut-based physical retiming algorithm for field programmable gate arrays
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Wire retiming as fixpoint computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we study the problem of retiming of sequential circuitswith both interconnect and gate delay. Most retiming algorithms haveassumed ideal conditions for the non-logical portions of the datapaths, which are not sufficiently accurate to be used in high performancecircuits today. In our modeling, we assume that the delay ofa wire is directly proportional to its length. This assumption is reasonablesince the quadratic component of a wire delay is significantlysmaller than its linear component when the more accurate Elmore delaymodel is used. A simple experiment is conducted to illustrate thevalidity of this assumption. We present two approaches to solve thisproblem, both of which have polynomial time complexity. The firstone can compute the optimal clock period while the second one isan improvement over the first one in terms of practical applicability.The second approach gives solutions very close to the optimal (0.13%more than the optimal on average) but in a much shorter runtime.A circuit with more than 22K gates and 32K wires can be optimallyretimed in 83.56 seconds by a PC with an 1.8GHz Intel Xeon processor.