Simultaneous circuit partitioning/clustering with retiming for performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Performance-optimal clustering with retiming for sequential circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Performance driven multiway partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Performance-driven multi-level clustering with application to hierarchical FPGA mapping
Proceedings of the 38th annual Design Automation Conference
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Global clustering-based performance-driven circuit partitioning
Proceedings of the 2002 international symposium on Physical design
Timing closure based on physical hierarchy
Proceedings of the 2002 international symposium on Physical design
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel global placement with retiming
Proceedings of the 40th annual Design Automation Conference
Performance-driven register insertion in placement
Proceedings of the 2004 international symposium on Physical design
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Retiming with Interconnect and Gate Delay
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Performance-driven global placement via adaptive network characterization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire retiming as fixpoint computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF's) and clustering the combinational part of the sequential circuit. This approach breaks the signal dependencies and assumes the positions of FF's are fixed. The positions of the FF's in a sequential circuit are in fact dynamic, because of retiming. As a result, current algorithms can only consider a small portion of the whole solution space. In this paper, we present a clustering algorithm that does not segment circuits by removing FF's. In additional, it considers the effect of retiming. The algorithm can produce clustering solutions with the optimal clock period under the unit delay model. For the general delay model, it can produce clustering solutions with a clock period provably close to optimal