Introduction to algorithms
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A fresh look at retiming via clock skew optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Spec Based Flip-Flop And Buffer Insertion
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Performance-driven register insertion in placement
Proceedings of the 2004 international symposium on Physical design
Retiming with Interconnect and Gate Delay
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Deriving a new efficient algorithm for min-period retiming
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating interconnect, register, and clock distribution delays into the retiming process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal clock period clustering for sequential circuits with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous routing and buffer insertion with restrictions on buffer locations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal path routing in single- and multiple-clock domain systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming for wire pipelining in system-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
Design closure driven delay relaxation based on convex cost network flow
Proceedings of the conference on Design, automation and test in Europe
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In system-on-chips (SOCs), a nonnegligible part of operation time is spent on global wires with long delays. Retiming-that is moving flip-flops in a circuit without changing its functionality-can be explored to pipeline long interconnect wires in SOC designs. The problem of retiming over a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be inserted on some wire segments is called the wire retiming problem. In this paper, we formulate the constraints of the wire retiming problem as a fixpoint computation and use an iterative algorithm to solve it. Experimental results show that this approach is multiple orders more efficient than the previous one.