Net weighting to reduce repeater counts during placement
Proceedings of the 42nd annual Design Automation Conference
Spec-based flip-flop and latch repeater planning
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Wire retiming as fixpoint computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability-constrained multi-bit flip-flop construction for clock power reduction
Integration, the VLSI Journal
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Efficient algorithms for the automatic insertion of flip-flops andbuffers are presented. The algorithms have been implemented as partof an automatic repeater insertion tool. The algorithms use adynamic programming framework to build viable solution pairs andthen pick the most optimal solution at the driver. Pruning rules tolimit the size of the solution space are also presented.