A mixed-integer linear programming problem which is efficiently solvable
Journal of Algorithms
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
Integration, the VLSI Journal
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Proceedings of the conference on Design, automation and test in Europe
Spec Based Flip-Flop And Buffer Insertion
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Exploiting level sensitive latches in wire pipelining
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Wave-pipelined on-chip global interconnect
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A methodology for optimal repeater insertion in pipelined interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient techniques to insert flip-flops and latches to meet pre-determined latency and margin constraints at the receivers. Previous approaches push timing margins to either ends of interconnect. We present an O(n log n)-time algorithm to insert flip-flops that evens out timing margins across the entire interconnect, resulting in more robust designs and faster design convergence. An O(n log n)-time extension to handle symmetric, two-phases latches is also presented. Experimental results verify the correctness and practicality of our approach.