Exploiting level sensitive latches in wire pipelining

Authors:
V. Seth;Min Zhao;Jiang Hu
Affiliations:
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA;Tabula Inc., Santa Clara, CA, USA;Dept. of ECE, Northwestern Univ., Evanston, IL, USA
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

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Abstract

Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are mostly based on edge triggered flip-flops. In this paper, we demonstrate the advantages of using level sensitive latches in terms of both latency and area cost. The input-output timing coupling and the strict short path constraint for latches demand additional design elaborations compared with flip-flops. New approaches are proposed in this work to solve these difficulties so that the advantages of latches can be fully utilized. In particular, a deferred delay padding technique is developed to correct short path violations with the minimal extra cost. These techniques are integrated with a dynamic programming based concurrent synchronous element and repeater insertion framework. Experimental results confirm the advantages of using latches as well as effectiveness of our algorithms.