Analysis of power dissipation in double edge-triggered flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Methodologies and Tools for Pipelined On-Chip Interconnect
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Proceedings of the conference on Design, automation and test in Europe
A method for correcting the functionality of a wire-pipelined circuit
Proceedings of the 41st annual Design Automation Conference
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Architecture-level synthesis for automatic interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Exploiting level sensitive latches in wire pipelining
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Microarchitecture evaluation with floorplanning and interconnect pipelining
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Retiming for wire pipelining in system-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved ber performance in intra-chip rf/wireless interconnect systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication--a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth analysis of the reliability in terms of bit error rate (BER) and the power consumption of wire-pipelining scheme. In this analysis, the dependencies of power consumption and BER on the number of inserted flip-flops, and the size of repeaters are illustrated. To trade off the design targets (wire delay, BER, and power consumption), a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. The methodology is demonstrated by calculating optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.