Error control systems for digital communication and storage
Error control systems for digital communication and storage
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Wireless Communications
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems
Microelectronics Journal
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Increasing operating frequency of current and future VLSI systems is putting physical constraint on hard-wired metal interconnect. Several revolutionary approaches to interconnect have been proposed. One of the most feasible approaches is RF/wireless interconnects. This paper evaluates the bit-error-rate (BER) performance of a coherent binary phase-shift keying (BPSK) with linear and systematic channel coding in an intra-chip RF/wireless interconnect system. The results indicate that for a certain range of received signal-to-noise (SNR) ratio, channel coding improves the performance of the RF/wireless interconnect system. Digital implementation of the encoder and decoder circuit block is also shown.