Analysis of power dissipation in double edge-triggered flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Methodologies and Tools for Pipelined On-Chip Interconnect
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Retiming for wire pipelining in system-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved ber performance in intra-chip rf/wireless interconnect systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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This paper addresses the problem of interconnect pipelining from both power consumption and bit error rate (BER) point of view and tries to find the optimal solution for a given wire pipelining scheme in nanometer scale very large scale integration technologies. In this paper a detailed analysis for the dependency of power consumption and BER on the number of flip-flops inserted and repeater size is performed. For the best tradeoff between the wire delay, BER and power consumption, a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. Then this methodology is applied to calculate the optimal solutions for some International Technology Roadmap for Semiconductor technology nodes.