Deriving a new efficient algorithm for min-period retiming
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
Design closure driven delay relaxation based on convex cost network flow
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire retiming as fixpoint computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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At the integration scale of system-on-chips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple-clock period wires. In this paper, we explore retiming to pipeline long interconnect wires in SOC designs. Behaviorally, it means that both computation and communication are rescheduled for parallelism. The retiming is applied to a netlist of macroblocks, where the internal structures may not be changed and flip-flops may not be able to be inserted on some wire segments. This problem is different from that on a gate-level netlist and is formulated as a wire-retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. Experimental results showed the benefits and effectiveness of our approach.