Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Asymptotically efficient retiming under setup and hold constraints
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Simultaneous circuit partitioning/clustering with retiming for performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Integration of retiming with architectural floorplanning
Integration, the VLSI Journal - Special issue on timing closure
Minimum-power retiming for dual-supply CMOS circuits
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Retiming of Circuits with Single Phase Transparent Latches
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel global placement with retiming
Proceedings of the 40th annual Design Automation Conference
Performance-driven register insertion in placement
Proceedings of the 2004 international symposium on Physical design
Retiming with Interconnect and Gate Delay
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Deriving a new efficient algorithm for min-period retiming
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wire retiming as fixpoint computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating interconnect, register, and clock distribution delays into the retiming process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal clock period clustering for sequential circuits with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing large multiphase level-clocked circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal path routing in single- and multiple-clock domain systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming for wire pipelining in system-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient incremental algorithm for min-area retiming
Proceedings of the 45th annual Design Automation Conference
Simultaneous slack budgeting and retiming for synchronous circuits optimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Network flow-based simultaneous retiming and slack budgeting for low power design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous work [17], which computed the minimum clock period in O(|V|3|E|lg|V|) time, our algorithm solves the same problem in O(|V|2|E|) time. Experimental results validate the efficiency of our algorithm.